--- cad/freehdl/Makefile.orig Fri Jun 8 18:07:15 2007 +++ cad/freehdl/Makefile Fri Jun 8 18:16:09 2007 @@ -9,7 +9,8 @@ PORTVERSION= 0.0.4 PORTREVISION= 1 CATEGORIES= cad -MASTER_SITES= http://cran.mit.edu/~enaroska/ +MASTER_SITES= http://www.home.hs-karlsruhe.de/~fado0011/ \ + http://cran.mit.edu/~enaroska/ MAINTAINER= lon_kamikaze@gmx.de COMMENT= A free VHDL simulator